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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a adv7123 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 cmos, 330 mhz t riple 10-bit high speed video dac functional block diagram r9?0 gnd r set ior ior comp adv7123 v ref voltage reference circuit g9?0 b9?0 iog iog iob iob psave power-down mode blank sync clock v aa dac 10 data register 10 dac 10 data register 10 dac 10 data register 10 blank and sync logic features 330 msps throughput rate triple 10-bit d/a converters sfdr C70 db at f clk = 50 mhz; f out = 1 mhz C53 db at f clk = 140 mhz; f out = 40 mhz rs-343a/rs-170 compatible output complementary outputs dac output current range 2 ma to 26 ma ttl compatible inputs internal reference (1.23 v) single-supply 5 v/3.3 v operation 48-lead lqfp package low power dissipation (30 mw min @ 3 v) low power standby mode (6 mw typ @ 3 v) industrial temperature range (C40 c to +85 c) applications digital video systems (1600 1200 @ 100 hz) high resolution color graphics digital radio modulation image processing instrumentation video signal reconstruction general description the adv7123 (adv ) is a triple high speed, digital-to-analog conver ter on a single monolithic chip. it consists of three high speed, 10-bit, video d/a converters with complementary outputs, a standard ttl input interface, and a high imped ance, analog output current source. the adv7123 has three separate 10-bit-wide input ports. a single 5 v/3.3 v power supply and clock are all that are required to make the part functional. the adv7123 has additional video control signals, composite sync and blank . the adv7123 also has a power-save mode. the adv7123 is fabricated in a 5 v cmos process. its mono- lithic cmos construction ensures greater functionality with lower power dissipation. the adv7123 is available in a 48-lead lqfp package. product highlights 1. 330 msps throughput 2. guaranteed monotonic to 10 bits 3. c ompatible with a wide variety of high resolution color graphics systems, including rs-343a and rs-170 adv is a registered trademark of analog devices, inc.
?2? rev. b adv7123especifications 5 v specifications parameter min typ max unit test conditions 1 static performance resolution (each dac) 10 bits integral nonlinearity (bsl) e1 ? ? ? ?
?3? rev. b adv7123 3.3 v specifications 1 parameter min typ max unit test conditions 2 static performance resolution (each dac) 10 bits r set = 680 ? ? ? ? ? ? ?
adv7123 ?4? rev. b 5 v dynamic specifications 1 parameter min typ max unit ac linearity spurious-free dynamic range to nyquist 2 single-ended output f clk = 50 mhz; f out = 1.00 mhz 67 dbc f clk = 50 mhz; f out = 2.51 mhz 67 dbc f clk = 50 mhz; f out = 5.04 mhz 63 dbc f clk = 50 mhz; f out = 20.2 mhz 55 dbc f clk = 100 mhz; f out = 2.51 mhz 62 dbc f clk = 100 mhz; f out = 5.04 mhz 60 dbc f clk = 100 mhz; f out = 20.2 mhz 54 dbc f clk = 100 mhz; f out = 40.4 mhz 48 dbc f clk = 140 mhz; f out = 2.51 mhz 57 dbc f clk = 140 mhz; f out = 5.04 mhz 58 dbc f clk = 140 mhz; f out = 20.2 mhz 52 dbc f clk = 140 mhz; f out = 40.4 mhz 41 dbc double-ended output f clk = 50 mhz; f out = 1.00 mhz 70 dbc f clk = 50 mhz; f out = 2.51 mhz 70 dbc f clk = 50 mhz; f out = 5.04 mhz 65 dbc f clk = 50 mhz; f out = 20.2 mhz 54 dbc f clk = 100 mhz; f out = 2.51 mhz 67 dbc f clk = 100 mhz; f out = 5.04 mhz 63 dbc f clk = 100 mhz; f out = 20.2 mhz 58 dbc f clk = 100 mhz; f out = 40.4 mhz 52 dbc f clk = 140 mhz; f out = 2.51 mhz 62 dbc f clk = 140 mhz; f out = 5.04 mhz 61 dbc f clk = 140 mhz; f out = 20.2 mhz 55 dbc f clk = 140 mhz; f out = 40.4 mhz 53 dbc spurious-free dynamic range within a window single-ended output f clk = 50 mhz; f out = 1.00 mhz; 1 mhz span 77 dbc f clk = 50 mhz; f out = 5.04 mhz; 2 mhz span 73 dbc f clk = 140 mhz; f out = 5.04 mhz; 4 mhz span 64 dbc double-ended output f clk = 50 mhz; f out = 1.00 mhz; 1 mhz span 74 dbc f clk = 50 mhz; f out = 5.00 mhz; 2 mhz span 73 dbc f clk = 140 mhz; f out = 5.00 mhz; 4 mhz span 60 dbc total harmonic distortion f clk = 50 mhz; f out = 1.00 mhz t a = 25 ? ?
?5? rev. b adv7123 3.3 v dynamic specifications parameter min typ max unit ac linearity spurious-free dynamic range to nyquist 2 single-ended output f clk = 50 mhz; f out = 1.00 mhz 67 dbc f clk = 50 mhz; f out = 2.51 mhz 67 dbc f clk = 50 mhz; f out = 5.04 mhz 63 dbc f clk = 50 mhz; f out = 20.2 mhz 55 dbc f clk = 100 mhz; f out = 2.51 mhz 62 dbc f clk = 100 mhz; f out = 5.04 mhz 60 dbc f clk = 100 mhz; f out = 20.2 mhz 54 dbc f clk = 100 mhz; f out = 40.4 mhz 48 dbc f clk = 140 mhz; f out = 2.51 mhz 57 dbc f clk = 140 mhz; f out = 5.04 mhz 58 dbc f clk = 140 mhz; f out = 20.2 mhz 52 dbc f clk = 140 mhz; f out = 40.4 mhz 41 dbc double-ended output f clk = 50 mhz; f out = 1.00 mhz 70 dbc f clk = 50 mhz; f out = 2.51 mhz 70 dbc f clk = 50 mhz; f out = 5.04 mhz 65 dbc f clk = 50 mhz; f out = 20.2 mhz 54 dbc f clk = 100 mhz; f out = 2.51 mhz 67 dbc f clk = 100 mhz; f out = 5.04 mhz 63 dbc f clk = 100 mhz; f out = 20.2 mhz 58 dbc f clk = 100 mhz; f out = 40.4 mhz 52 dbc f clk = 140 mhz; f out = 2.51 mhz 62 dbc f clk = 140 mhz; f out = 5.04 mhz 61 dbc f clk = 140 mhz; f out = 20.2 mhz 55 dbc f clk = 140 mhz; f out = 40.4 mhz 53 dbc spurious-free dynamic range within a window single-ended output f clk = 50 mhz; f out = 1.00 mhz; 1 mhz span 77 dbc f clk = 50 mhz; f out = 5.04 mhz; 2 mhz span 73 dbc f clk = 140 mhz; f out = 5.04 mhz; 4 mhz span 64 dbc double-ended output f clk = 50 mhz; f out = 1.00 mhz; 1 mhz span 74 dbc f clk = 50 mhz; f out = 5.00 mhz; 2 mhz span 73 dbc f clk = 140 mhz; f out = 5.00 mhz; 4 mhz span 60 dbc total harmonic distortion f clk = 50 mhz; f out = 1.00 mhz t a = 25 ? ?
adv7123 ?6? rev. b 5 v timing specifications 1 parameter min typ max unit condition analog outputs analog output delay, t 6 5.5 ns analog output rise/fall time, t 7 4 1.0 ns analog output transition time, t 8 5 15 ns analog output skew, t 9 6 12 ns clock control f clk 7 0.5 50 mhz 50 mhz grade f clk 7 0.5 140 mhz 140 mhz grade f clk 7 0.5 240 mhz 240 mhz grade data and control setup, t 1 0.5 ns data and control hold, t 2 1.5 ns clock pulsewidth high, t 4 1.875 ns f clk _ max = 240 mhz clock pulsewidth low t 5 1.875 ns f clk _ max = 240 mhz clock pulsewidth high t 4 2.85 ns f clk _ max = 140 mhz clock pulsewidth low t 5 2.85 ns f clk _ max = 140 mhz clock pulsewidth high t 4 8.0 ns f clk _ max = 50 mhz clock pulsewidth low t 5 8.0 ns f clk _ max = 50 mhz pipeline delay, t pd 6 1.0 1.0 1.0 clock cycles psave up time, t 10 6 210 ns notes 1 timing specifications are measured with input levels of 3.0 v (v ih ) and 0 v (v il ) 0 for both 5 v and 3.3 v supplies. 2 these maximum and minimum specifications are guaranteed over this range. 3 temperature range: t min to t max : e40 ?
?7? rev. b adv7123 3.3 v timing specifications 1 parameter min typ max unit condition analog outputs analog output delay, t 6 7.5 ns analog output rise/fall time, t 7 4 1.0 ns analog output transition time, t 8 5 15 ns analog output skew, t 9 6 12 ns clock control f clk 7 50 mhz 50 mhz grade f clk 7 140 mhz 140 mhz grade f clk 7 240 mhz 240 mhz grade f clk 7 330 mhz 330 mhz grade data and control setup, t 1 0.2 ns data and control hold, t 2 1.5 ns clock pulsewidth high, t 4 6 1.4 ns f clk_max = 330 mhz clock pulsewidth low, t 5 6 1.4 ns f clk_max = 330 mhz clock pulsewidth high, t 4 1.875 ns f clk_max = 240 mhz clock pulsewidth low t 5 1.875 ns f clk_max = 240 mhz clock pulsewidth high t 4 2.85 ns f clk_max = 140 mhz clock pulsewidth low t 5 2.85 ns f clk_max = 140 mhz clock pulsewidth high t 4 8.0 ns f clk_max = 50 mhz clock pulsewidth low t 5 8.0 ns f clk_max = 50 mhz pipeline delay, t pd 6 1.0 1.0 1.0 clock cycles psave up time, t 10 6 410 ns notes 1 timing specifications are measured with input levels of 3.0 v (v ih ) and 0 v (v il ) 0 for both 5 v and 3.3 v supplies. 2 these maximum and minimum specifications are guaranteed over this range. 3 temperature range: t min to t max : e40 ?
adv7123 ?8? rev. b absolute maximum ratings 1 v aa to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v voltage on any digital pin . . . . . gnd e 0.5 v to v aa + 0.5 v ambient operating temperature (t a ) . . . . . e40
adv7123 ?9? rev. b pin function descriptions pin no. mnemonic function 1e10 g0eg9 r0, g0, and b0 are the least significant data bits. unused pixel data inputs should be connected to either the regular pcb power or ground plane. 11 blank composite blank control input (ttl compatible). a logic zero on this control input drives the analog outputs, ior, iob, and iog, to the blanking level. the blank signal is latched on the rising edge of clock. while blank is a logical zero, the r0er9, g0eg9, and b0eb9 pixel inputs are ignored. 12 sync composite sync control input (ttl compatible). a logical zero on the sync input switches off a 40 ire current source. this is internally connected to the iog analog output. sync does not over- ride any other control or data input; therefore, it should only be asserted during the blanking interval. sync is latched on the rising edge of clock. if sync information is not required on the green channel, the sync input should be tied to logical zero. 13, 29, 30 v aa analog power supply (5 v ? ? ? ? ? ? ?
adv7123 ?10? rev. b terminology blanking level the level separating the sync portion from the video portion of the waveform. usually referred to as the front porch or back porch. at 0 ire units, it is the level that will shut off the picture tube, resulting in the blackest possible picture. color video (rgb) this usually refers to the technique of combining the three primary colors of red, green, and blue to produce color pictures within the usual spectrum. in rgb monitors, three dacs are required, one for each color. sync signal ( sync gs aac ac rs cr rbl rl sl sync s a
adv7123 ?11? rev. b 5 vetypical performance characteristics (v aa = 5 v, v ref = 1.235 v, i out = 17.62 ma, 50 doubly terminated load, differential output loading, t a = 25 c) f out e mhz 70 0 0.1 100 1 sfdr e dbc 2.51 5.04 20.2 40.4 60 50 40 20 10 30 sfdr (de) sfdr (se) tpc 1. sfdr vs. f out @ f clock = 140 mhz (single-ended and differential) f clock e mhz 74 58 thd e dbc 50 100 140 72 70 68 64 60 66 76 62 0 160 fourth harmonic third harmonic second harmonic tpc 4. thd vs. f clock @ f out = 2 mhz (second, third, and fourth harmonics) 0khz start e85.0 sfdr e dbm e45.0 e5.0 35.0mhz 70.0mhz stop tpc 7. single-tone sfdr @ f clock = 140 mhz (f out = 2 mhz) f out e mhz 70 0 0.1 100 1 sfdr e dbc 2.51 5.04 20.2 40.4 60 50 40 20 10 30 80 sfdr (se) sfdr (de) tpc 2. sfdr vs. f out @ f clock = 50 mhz (single-ended and differen tial) i out e ma 0.9 0 linearity e lsbs 2 17.62 0.8 0.7 0.6 0.4 0.2 0.5 1.0 0.3 020 0.1 tpc 5. linearity vs. i out 0khz start e85.0 sfdr e dbm e45.0 e5.0 35.0mhz 70.0mhz stop tpc 8. single-tone sfdr @ f clock = 140 mhz (f out1 = 20 mhz) temperature e c 71.8 70.4 sfdr e dbc +25 +85 71.6 71.4 71.2 70.8 70.6 71.0 72.0 e10 tpc 3. sfdr vs. temperature @ f clock = 50 mhz (f out = 1 mhz) code e inl e1.00 error e lsb 0.50 e0.50 0.00 1.00 0.75 1023 e0.16 tpc 6. typical linearity (inl) 0khz start e85.0 sfdr e dbm e45.0 e5.0 35.0mhz 70.0mhz stop tpc 9. dual-tone sfdr @ f clock = 140 mhz (f out1 = 13.5 mhz, f out2 = 14.5 mhz)
adv7123 ?12? rev. b 3 vetypical performance characteristics (v aa = 3 v, v ref = 1.235 v, i out = 17.62 ma, 50 doubly terminated load, differential output loading, t a = 25 c) f out e mhz 70 0 0.1 100 sfdr e dbc 2.51 5.04 20.2 40.4 60 50 40 20 10 30 sfdr (se) sfdr (de) tpc 10. sfdr vs. f out @ f clock = 140 mhz (single-ended and differential) frequency e mhz 74 58 thd e dbc 50 100 140 72 70 68 64 60 66 76 62 0 160 second harmonic third harmonic fourth harmonic tpc 13. thd vs. f clock @ f out = 2 mhz (second, third, and fourth harmonics) 0khz start e85.0 sfdr e dbm e45.0 e5.0 35.0mhz 70.0mhz stop tpc 16. single-tone sfdr @ f clock = 140 mhz (f out1 = 2 mhz) f out e mhz 70 0 0.1 100 1.0 sfdr e dbc 2.51 5.04 20.2 40.4 60 50 40 20 10 30 80 sfdr (se) sfdr (de) tpc 11. sfdr vs. f out @ f clock = 140 mhz (single-ended and differential) i out e ma 0.9 0 linearity e lsbs 2 17.62 0.8 0.7 0.6 0.4 0.2 0.5 1.0 0.3 020 0.1 tpc 14. linearity vs. i out 0khz start e85.0 sfdr e dbm e45.0 e5.0 35.0mhz 70.0mhz stop tpc 17. single-tone sfdr @ f clock = 140 mhz (f out1 = 20 mhz) temperature e c 71.8 70.4 sfdr e dbc 20 85 145 71.6 71.4 71.2 70.8 70.6 71.0 72.0 165 0 tpc 12. sfdr vs. temperature @ f clock = 50 mhz, (f out = 1 mhz) code e inl e1.00 linearity e lsb 0.50 e0.50 0.00 1.00 0.75 1023 e0.42 tpc 15. typical linearity 0khz start e85.0 sfdr e dbm e45.0 e5.0 35.0mhz 70.0mhz stop tpc 18. dual-tone sfdr @ f clock = 140 mhz (f out1 = 13.5 mhz, f out2 = 14.5 mhz)
adv7123 ?13? rev. b circuit description and operation the adv7123 contains three 10-bit d/a converters, with three input channels, each containing a 10-bit register. also integrated on board the part is a reference amplifier. crt con trol func tions blank and sync are integrated on board the adv7123. digital inputs thirty bits of pixel data (color information) r0er9, g0eg9, and b0eb9 are latched into the device on the rising edge of each clock cycle. this data is presented to the three 10-bit dacs and then converted to three analog (rgb) output waveforms. see figure 2. clock data analog outputs ( ior, iog, iob ior , iog , iob ) digital inputs (r9er0, g9eg0, b9eb0, sync , blank ) figure 2. video data input/output the adv7123 has two additional control signals that are latched to the analog video outputs in a similar fashion. blank and sync are each latched on the rising edge of clock to maintain synchronization with the pixel data stream. the blank and sync functions allow for the encoding of these video synchronization signals onto the rgb video output. this is done by adding appropriately weighted current sources to the analog outputs, as determined by the logic levels on the blank and sync digital inputs. figure 3 shows the analog output, rgb video waveform of the adv7123. the influence of sync and blank on the analog video waveform is illustrated. table i details the resultant effect on the analog outputs of blank and sync . all these digital inputs are specified to accept ttl logic levels. clock input the clock input of the adv7123 is typically the pixel clock rate of the system. it is also known as the dot rate. the dot rate, and thus the required clock frequency, will be determined by the on-screen resolution according to the following equation: dot rate = ( horiz res ) vert res ) refresh rate )/ ( retrace factor ) horiz res =n umber of pixels/line. vert res =n umber of lines/frame. refresh rate =h orizontal scan rate. this is the rate at which the screen must be refreshed, typically 60 hz for a noninterlaced system or 30 hz for an interlaced system. retrace factor =t otal blank time factor. this takes into account that the display is blanked for a certain fraction of the total duration of each frame (e.g., 0.8). table i. video output truth table (r set = 530 , r load = 37.5 ) dac description iog (ma) iog a ioriob ior iob sync blank i ill io io blank blackll black blank blank ll sync ll rbl grn a a ill blank ll sync ll ir ir nos osconncoaoblyrina loa r r s rsallsanolrancsassonalllls rgbo
adv7123 ?14? rev. b therefore, if we have a graphics system with a 1024 iog * ( ma ) = 11,445 v ref (v)/ r set ( ? ior, iob (ma) = 7,989.6 v ref (v)/r set ( ? ? ? ? ? ? ? ? ? video formats & required load terminations available from analog devices, pub- lication no. e1228e15e1/89. figure 3 shows the video waveforms associated with the three rgb outputs driving the doubly terminated 75 ? ? ? ?
adv7123 ?15? rev. b ground planes the adv7123, and associated analog circuitry, should have a separate ground plane referred to as the analog ground plane. this ground plane should connect to the regular pcb ground plane at a single point through a ferrite bead, as illustrated in figure 7. this bead should be located as close as possible (within three inches) to the adv7123. the analog ground plane should encompass all adv7123 ground pins, voltage reference circuitry, power supply bypass circuitry, the analog output traces, and any output amplifiers. the regular pcb ground plane area should encompass all the digital signal traces, excluding the ground pins, leading up to the adv7123. power planes the pc board layout should have two distinct power planes, one for analog circuitry and one for digital circuitry. the analog power plane should encompass the adv7123 (v aa ) and all associated analog circuitry. this power plane should be con- nected to the regular pcb power plane (v cc ) at a single point through a ferrite bead, as illustrated in figure 7. this bead sh ould be loc ated within three inc hes of the adv7123. the pcb power plane should provide power to all digital logic on the pc board, and the analog power plane should provide power to all adv7123 power pins, voltage reference circuitry, and any output amplifiers. the pcb power and ground planes should not overlay portions of the analog power plane. keeping the pcb power and ground planes from overlaying the analog power plane will contribute to a reduction in plane-to-plane noise coupling. supply decoupling noise on the analog power plane can be further reduced by the use of multiple decoupling capacitors (see figure 7). optimum performance is achieved by the use of 0.1
adv7123 ?16? rev. b any active pull-up termination resistors for the digital inputs should be connected to the regular pcb power plane (v cc ) and not the analog power plane. analog signal interconnect the adv7123 should be located as close as possible to the output connectors, thus minimizing noise pickup and reflections due to impedance mismatch. the video output signals should overlay the ground plane and not the analog power plane, thereby maximizing the high fre- quency power supply rejection. gnd r set ior iog iob adv7123 75 comp complementary outputs r9er0 g9 eg0 b9 eb0 clock sync psave video data inputs analog ground plane l1 (ferrite bead) v aa v ref r set 530 ior iog iob 75 75 blank 75 75 75 0.1 f 0.1 f 10 f 0.01 f 33 f 0.1 f 5v (v aa ) power supply decoupling (0.1 f and 0.01 f capacitor for each v aa group) coaxial cable 75 13, 29, 30 25, 26 39-48 1-10 14-23 monitor (crt) bnc connectors 5v (v aa ) v cc v aa figure 7. typical connection diagram for optimum performance, the analog outputs should each have a source terminat ion resistance to ground of 75 ? ? design and layout of a video graphics system for reduced emi . this application note is available from analog devices, publication no. e1309e15e10/89.
adv7123 ?17? rev. b 48-lead plastic quad flatpack [lqfp] 1.4 mm thick (st-48) dimensions shown in millimeters top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc 7.00 bsc seating plane 1.60 max 0.75 0.60 0.45 view a 7 3.5 0 0.20 0.09 1.45 1.40 1.35 0.15 0.05 0.08 max coplanarity view a rotated 90 ccw pin 1 indicator 9.00 bsc compliant to jedec standards ms-026bbc seating plane outline dimensions
adv7123 ?18? rev. b revision history location page 10/02?data sheet changed from rev. a to rev. b. change in title . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 change to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 change to product highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 change specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 change to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 change to pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 change to reference input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 change to figure 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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C20C c00215C0C10/02(b) printed in u.s.a.

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